1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and in particular relates to a method of fabricating a semiconductor device having special features in the method of forming transistors in an IC including memory cells.
2. Description of the Related Art
The circuitry within a single chip of a memory typified by a DRAM (Dynamic Random Access Memory) can be broadly classified into the memory cell section and peripheral circuitry section. In the case of a DRAM, since, in the transistors in the memory cells, a capacitor is formed on one side of the source/drain region, a high charge-holding performance is demanded. On the other hand, in the transistors of the peripheral circuitry, high current drive capability is demanded in order to achieve high operating speeds. LDD (Lightly Doped Drain) transistors etc. are known as a way of satisfying these demands simultaneously, being claimed to have both high reliability and high current drive capability. In order to form LDD transistors etc. it is necessary to form a side wall on the insulating film on the side face of the gate electrode. However, there is the problem that, when etching in the formation of this sidewall, the diffusion layer in the memory cell is exposed to the etching atmosphere, resulting in the formation of crystal defects. As a result, the charge holding performance is impaired. In order to solve this problem, a method has been proposed whereby, after transistor formation, the transistor surfaces within the memory cells only are covered with insulating film, while the transistor surfaces of the peripheral circuitry section are not covered with insulating film. An example is the method shown in FIG. 12 to FIG. 19 (see Japanese Patent Publication No. H.8-21687).
FIG. 12 to FIG. 19 are cross-sectional views showing a first prior art example. In these Figures, (a), (b) and (c) respectively show the interior of a memory cell, the peripheral circuitry section (Nch), and peripheral circuitry section (Pch).
First of all, as shown in FIG. 12, a field oxide film 2 is formed by the ordinary method of selective oxidation (LOCOS: Local Oxidation of Silicon) etc. on a P-type semiconductor substrate 1. After formation of gate oxide film 3 on the element active regions defined by the field oxide film 2, a conductive film such as for example polysilicon film or tungsten silicide film of film thickness about 200 [nm] for example is grown on the entire surface.
Gate electrodes 4 are formed by patterning this conductive film in a prescribed shape. Then, resist is formed only on the peripheral circuitry section (Pch) and, by for example injection of impurity such as phosphorus, a N-diffusion layer 5 is formed only in the diffusion layer section within the memory cells and peripheral circuitry section (Nch) followed by removal of the resist.
Next, as shown in FIG. 13, a silicon oxide film 6 of film thickness for example about 100 [nm] is grown over the entire surface. Next, as shown in FIG. 14, resist is formed only above the interior of the memory cells and etching of the silicon oxide film 6 is performed, after which the resist is removed. In this way, a condition is produced in which silicon oxide film 6 remains behind on the entire surface in the memory cells whereas, in the case of the peripheral circuitry section, silicon oxide film side walls 8 are formed at the side faces of the gates.
Next, as shown in FIG. 15, a silicon oxide film 25 of film thickness about 200 [nm] for example is formed on the entire surface. Next, as shown in FIG. 16, etching of silicon oxide film 25 is performed and silicon oxide film side walls 26 are formed. Next, resist is formed over the interior of the memory cells and the peripheral circuitry section (Pch) and then, for example injection of impurities such as phosphorus or arsenic, N+ diffusion layer 10 is formed only on peripheral circuitry section (Nch). In addition, a P+ diffusion layer 11 is formed only on peripheral circuitry section (Pch) by injection of impurities such as for example boron or BF.sub.2 after formation of resist over the interior of the memory cells and the peripheral circuitry section (Nch).
In addition, as shown in FIG. 17, an inter-layer insulating film 12 such as silicon oxide film containing for example phosphorus or boron of thickness for example about 300 [nm] is grown over the entire surface. After this, apertures are formed in prescribed regions in the memory cells, and a buried conductive film 13 such as polysilicon containing for example phosphorus is formed within the aperture sections. Then, a conductive film such as tungsten silicide film of thickness for example about 200 [nm] is grown over the entire surface and bit lines 14 are formed by patterning this conductive film.
Then, as shown in FIG. 18, after growing over the entire surface an inter-layer insulating film 15 such as silicon oxide film containing phosphorus or boron of film thickness for example about 300 [nm], aperture sections are formed in prescribed regions of inter-layer insulating film 15. Further, by growing a conductive film such as polysilicon containing phosphorus of for example film thickness about 600 [nm] over the entire surface and patterning into the prescribed shape, capacitor lower electrodes 16 are formed.
Next, as shown in FIG. 19, capacitor insulating film 17 such as silicon nitride film of thickness for example about 6 [nm] is grown over the entire surface and then the capacitor upper electrodes 18 are formed, only within the memory cells, by growing conductive film such as polysilicon containing phosphorus of thickness for example about 200 [nm] over the entire surface, followed by patterning. Furthermore, an inter-layer insulating film 19 produced by a composite film of silicon oxide film containing for example phosphorus and boron and non-doped silicon oxide film is grown over the entire surface and aperture sections are then formed in prescribed regions of the peripheral circuitry section. After forming a buried conductive film 20 by a conductive film such as for example tungsten in the interior of the aperture sections, a film such as aluminium or titanium nitride containing for example titanium, titanium nitride, silicon or copper is successively formed, followed by patterning, to form low-resistance wiring 21.
The basic portions of the interior of the memory cells and the peripheral circuitry section of the DRAM can thus be formed as described above. With this first prior art example, since insulating film side walls can be formed on the side face of gate electrodes 4 in the peripheral circuitry section, LDD transistors can be formed in the Nch section while BC-LDD (Buried Channel LDD) transistors can be formed in the Pch section. This makes it possible to improve the reliability of the transistor and to obtain high current drive capability. Also, within the memory cells, since the memory cells are covered by insulating film, the N.sup.- diffusion layer 5 within the memory cells is not exposed to the etching atmosphere, so generation of crystal defects is suppressed, and the charge-holding performance of the memory cells can be improved.
Next, a second prior art example will be described. In the second prior art example, the current drive capability of the transistors is further improved by employing the conventional method of titanium siliciding of the diffusion layer section in the first prior art example. An example of this is the method shown in FIG. 20 to FIG. 24.
First of all, as shown in FIG. 20, a field oxide film 2 is formed on the P.sup.- type semiconductor substrate 1 by the ordinary method of selective oxidation (LOCOS), for example. After forming gate oxide film 3 on the element active regions defined by the field oxide film 2, a conductive film such as polysilicon film or tungsten silicide of thickness for example 200 [nm] is grown over the entire surface, and gate electrodes 4 are formed by patterning this conductive film to the prescribed shape. Next, a resist is formed only on the peripheral circuitry section (Pch) and N.sup.- diffusion layer 5 is formed only in the diffusion layer section of the interior of the memory cells and the peripheral circuitry section (Nch) by injection of impurity such as for example phosphorus, after which the resist is removed.
Next, a silicon nitride film 27 is grown over the entire surface with a thickness of for example about 100 [nm], as shown in FIG. 21.
Next, silicon nitride film side walls 22 are formed on the side faces of the gate electrodes 4 by performing etching of silicon nitride film 27 as shown in FIG. 22. Next, a N+ diffusion layer 10 is formed only on the peripheral circuitry section (Nch) by injection of impurities such as for example phosphorus or arsenic after forming a resist over the interior of the memory cells and the peripheral circuitry section (Pch).
Furthermore, after forming a resist over the interior of the memory cells and the peripheral circuitry section (Nch), a P+ diffusion layer 11 is formed only in the peripheral circuitry section (Pch) by performing injection of impurity such as for example boron or BF.sub.2.
Next, as shown in FIG. 23, titanium having a film thickness of about 80 nm, example, is grown on the entire surface by the sputtering method and heat treatment is performed under a nitrogen atmosphere. Further, unreacted titanium is removed by a mixed liquid of sulphuric acid and hydrogen peroxide. In this way, a titanium silicide film 23 is formed on the gates and a titanium silicide film 24 is formed on the diffusion layers. Although in this case titanium silicide is formed on the diffusion layers, this could be a film of silicide consisting of silicon and a transition metal element such as cobalt silicide. Such a reaction is generally termed saliciding (salicide: abbreviation of Self-Aligned Silicide)
Next, as shown in FIG. 24, an inter-layer insulating film 12 such as silicon oxide film containing for example phosphorus or boron of for example film thickness about 300 [nm] is grown over the entire surface. After this, apertures are formed in prescribed regions within the memory cells, and a buried conductive film 13 such as polysilicon containing for example phosphorus is formed within the aperture section. A conductive film such as tungsten silicide film is grown over the entire surface in a thickness of for example 200 [nm] and then subjected to patterning to form bit lines 14. Then, an inter-layer insulating film 15 such as silicon oxide film containing phosphorus and/or boron of for example film thickness about 300 [nm] is grown over the entire surface, after which aperture sections are formed in prescribed regions of inter-layer insulating film 15. Furthermore, conductive film such as polysilicon containing phosphorus of for example film thickness about 600 [nm] is grown over the entire surface, then patterned to the prescribed shape to form capacitor lower electrodes 16. Then, capacitor insulating film 17 such as silicon nitride film of thickness for example 6 [nm] is grown over the entire surface, after which the capacitor upper electrodes 18 are formed only within the memory cells by patterning after growing conductive film such as polysilicon containing phosphorus of or example film thickness 200 [nm] over the entire surface.
Further, inter-layer insulating film 19 produced using a composite film of silicon oxide film containing for example phosphorus and boron and non-doped silicon oxide film is grown over the entire surface and aperture sections are then formed in prescribed regions of the peripheral circuitry section. A buried conductive film 20 produced by conductive film such as tungsten, for example, is formed within the aperture sections and a film such as aluminium or tungsten nitride containing for example titanium, titanium nitride, silicon or copper is then successively formed and subjected to patterning to form low-resistance wiring 21.
With this second prior art example, improvement in the current drive capability is obtained by saliciding the top of the diffusion layer. Also, lowering of the resistance of the gate electrodes is achieved by saliciding the top of the gate electrodes.
However, these prior art examples are subject to the following problems.
The first problem relates to the first prior art example. Specifically, when silicon oxide film side wall 8 is formed on the side face of the gate electrodes of the peripheral circuitry section, it is necessary to cover the interior of the memory cells by a resist in order that the interior of the memory cells should not be exposed to the etching atmosphere. This therefore necessitates increase of the number of steps by one in each case for the lithography and oxide film etching, respectively, as well as construction of a reticle for the lithography.
The second problem relates to the second prior art example. Specifically, a deep junction must be formed in the N.sup.- diffusion layer 5 within the memory cells in order to withstand saliciding of the diffusion layer. This therefore tends to produce the effect of shortening the channels of the transistor, which is disadvantageous in regard to reducing the overall size of the DRAM memory cell. Also, the number of defects is increased by saliciding of the N.sup.- diffusion layer 5, increasing junction leakage of the N.sup.- diffusion layer 5 section. Deterioration of the charge-holding performance of the memory cell therefore occurs.